Typically, a computer system includes a number of integrated circuit chips that communicate with one another to perform system applications. Often, the computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The controller and memory communicate with one another to store data and to read the stored data.
The memory chips can be any suitable type of memory including RAM, which can be any suitable type of RAM, such as dynamic RAM (DRAM). DRAM typically includes a plurality of memory banks. Each memory bank includes one or more arrays of memory cells. The memory cells in each array of memory cells are arranged in rows and columns, with the rows extending along a row direction and the columns extending along a column direction. Conductive word lines and bit lines extend across the array of memory cells, with a memory cell located at each cross-point of a word line and a bit line or located at each second cross-point for example. Memory cells are accessed using a row address and a column address.
Each of the memory cells in an array of memory cells includes a capacitor and a transistor. The capacitor is electrically coupled through the transistor to one of the bit lines. The control input of the transistor is electrically coupled to one of the word lines. The transistor is switched on (conducting) to access the capacitor and off (non-conducting) to capture a voltage level on the capacitor via the appropriate word line. The capacitor is charged to a high voltage level that can represent a logic one or discharged to a low voltage level that can represent a logic zero.
During a precharge operation, a pair of bit lines are equalized to a common voltage level. In known memory systems, the bit line pair is coupled together and a precharge voltage is applied to the bit lines via one or more limit transistors, which among other things, limits the precharge current supplied by a voltage source during the equalization/precharge operation. Following the precharge operation during a BANKACTIVATE operation, one of the bit lines of the bit line pair receives a data bit value from a memory cell activated by the corresponding word line and the other bit line is used as a reference. To read the data bit, a sense amplifier amplifies the difference between the data bit value and the reference value and provides a sensed output value to an output driver. To write a data bit into a selected memory cell, input drivers overdrive the sense amplifier. One input driver overdrives a data bit value onto the bit line that is connected to the selected memory cell and another input driver overdrives the inverse of the data bit value onto the reference bit line.
Short-circuits can occur between word lines and bit lines in devices such as DRAMs. This is especially problematic in the precharge operations. To remedy this, the sense amplifier includes the limit transistors that function to limit current resulting from these short-circuits. The provision of the limit transistors, however, increases the size of the sense amplifier, and in turn, uses additional chip surface. Still further, the provision of such limit transistors may not adequately limit all of the undesirable short-circuit current in all situations.
For these and other reasons, there is a need for the present invention.